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es_lpc2368 errata sheet lpc2368 rev. 9 ? 20 april 2011 errata sheet document information info content keywords lpc2368 errata abstract this errata sheet describes both the known functional problems and any deviations from the electrical specific ations known at t he release date of this document. each deviation is assigned a number and its history is tracked in a table at the end of the document.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 2 of 18 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors es_lpc2368 errata sheet lpc2368 revision history rev date description 9 20110420 ? added note.2. 8 20110301 ? added adc.2. 7 20100401 ? the format of this errata sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? added ethernet.4 6 20100122 ? added vbat.2 5 20090512 ? added rev d 4 20080602 ? added errata note.1 3 20080408 ? added vbat.1 2 20070921 ? added rev b ? removed rev a from esd.1. esd.1 does not appear in rev a. it was accidentally listed in version 1.3 1 20070720 ? added ethernet.3 ? added deep power down mode.1 ? updated flash.1 ? updated ethernet.1
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 3 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 1. product identification the lpc2368 devices typically have the following top-side marking: lpc2368xxx xxxxxxx xxyywwr[x] the last/second to last letter in the third line (field ?r?) will identify the device revision. this errata sheet covers the following revisions of the lpc2368: field ?yy? states the year the device was manufactured. field ?ww? states the week the device was manufactured during that year. 2. errata overview table 1. device revision table revision identifier (r) revision description ?-? initial device revision ?a? second device revision ?b? third device revision ?d? fourth device revision table 2. functional problems table functional problems short description revision identifier detailed description ethernet.4 ether net txconsumeindex register does not update correctly after the first frame is sent ?-?, ?a?, ?b?, ?d? section 3.1 on page 5 adc.1 addrx read conflicts with hardware setting of done bit ?-? section 3.2 on page 5 ethernet.1 setting up the ether net interface in rmii mode ?-? section 3.3 on page 6 ethernet.2 ethe rnet sram disabled ?-? section 3.4 on page 7 ethernet.3 rxdescriptor number cannot be greater than 4 ?-? section 3.5 on page 7 i2s.1 i 2 s dma can stall ?-? section 3.6 on page 7 pll.1 pll output is limited to 290 mhz ?-? section 3.7 on page 8 sram.1 16 kb sram can not be used for code execution ?-? section 3.8 on page 8 usb.1 usb_need_clk is always asserted ?-? section 3.9 on page 9 usb.2 u1connect is not functional ?-? section 3.10 on page 9 usb.3 v bus status input is not functional ?-? section 3.11 on page 9 wdt.1 accessing non-watchdog apb registers in the middle of the feed sequence causes a reset ?-? section 3.12 on page 10 core.1 incorrect update of the abort link register in thumb state ?-?, ?a?, ?b?, ?d? section 3.13 on page 10 flash.1 operating speed out of on-c hip flash is restricted ?-?, ?a? section 3.14 on page 11 mam.1 code execution failure can occur with mam mode 2 ?-?, ?a? section 3.15 on page 12 can.1 data overrun condition can lock the can controller ?-?, ?a?, ?b? section 3.16 on page 12
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 4 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 deep power-down.1 deep power-down mode is not functional ?-?, ?a?, ?b? section 3.17 on page 13 vbat.1 increased power consumption on vbat when vbat is powered before the 3.3 v s upply used by rest of device ?-?, ?a?, ?b? section 3.18 on page 13 vbat.2 the vbat pin cannot be left floating ?-?, ?a?, ?b? section 3.19 on page 13 adc.2 external sync inputs not operational ?-?, ?a?, ?b?, ?d? section 3.20 on page 14 table 2. functional problems table ?continued functional problems short description revision identifier detailed description table 3. ac/dc deviations table ac/dc deviations short description product version(s) detailed description esd.1 2 kv esd requirements are not met on the rtcx1 pin ?-? section 4.1 on page 15 table 4. errata notes table errata notes short description revision identifier detailed description note.1 when the input voltage is vi ? v dd i/o + 0.5 v on each of the following port pins p0.23, p0.24. p0.25, p0.26, p1.30, and p1.31 (configured as general purpose input pin (s)), current must be limited to less than 4 ma by using a series limiting resistor. ?-?, ?a?, ?b?, ?d? section 5.1 on page 15 note.2 on the lpc2368 rev d, design changes to the memory accelerator module were made to enhance timing and general performance. ?d? section 5.2 on page 15
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 5 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 3. functional problems detail 3.1 ethernet.4: ethernet txconsum eindex register does not update correctly after the first frame is sent introduction: the transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmit process. af ter a frame has been transmitted hardware increments the index, wrapping the value to 0 once the value of txdescriptornumber has been reached. if the txconsumeindex equa ls txproduceindex the descriptor array is empty and the transmit channel will stop tr ansmitting until software produces new descriptors. problem: the txconsumeindex register is not updated correc tly (from 0 to 1) after the first frame is sent. after the next frame sent, the txconsumei ndex register is updated by two (from 0 to 2). this only happens the very first time, so subsequent updates are correct (even those from 0 to 1, after wrapping the value to 0 once the value of txdesc riptornumber has been reached) work-around: software can correct this situation in many ways; for example, sending a dummy frame after initialization. 3.2 adc.1: addrx read conflicts wit h hardware setting of the done bit introduction: the lpc2368 has a 10-bit adc, which c an be used to measure analog signals and convert the signals into a 10-bit digital result. there are eight a/d channels and each channel has its own individual a/d data r egister (addr0 to addr7). the a/d data register holds the result when an a/d conversion is complete, and also includes the flags that indicate when a conversion has been completed (done bit) and when a conversion overrun has occurred. the done bit is clear ed when the respective a/d data register is read. problem: if a software read of addrx conflicts with th e hardware setting of the done bit in the same register (once a conversion is co mpleted) then the done bit gets cleared automatically, thereby clearing the indication that a conversion was completed. work-around: for software controlled mode or burst mode with only one channel selected, the done bit in the a/d global data register (located at 0xe003 4004) can be used instead of the individual addrx result register with no impact on performance. for burst mode with mu ltiple channels selected, the done bit together with the chn field in the a/d global data register can be used with some impact on throughput.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 6 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 3.3 ethernet.1: setting up the et hernet interface in rmii mode introduction: the lpc2368 has an ethernet interface, which can be interfaced with an off-chip phy using the rmii interface. problem: the default configuration of the device does not enable the rmii interface. work-around: to use the ethernet interface in rmii mode write a 1 to bit 12 (p1.16) in pinsel2 register (located at 0xe002 c008). th is workaround only applies for rev ?-? devices and does not apply for rev ?a? and newer devices. in order to have both rev ?-? and other revisions coexist in the same piece of software, the mac module id can be used to identify the part and determine if port pin p1.6 needs to be set or not. here are the steps (along with some sample code) to initialize the mac based on the module id: 1. in master header file llpc24xx.h, make sure module id is defined (please note, this id register is not documented in the user's manual). #define mac_base_addr 0xffe00000 #define mac_moduleid (*(volatile unsigned long *)(mac_base_addr + 0xffc)) /* module id reg (ro) */ 2. in the beginning of the mac init ialization file, a dd below definition: #define old_emac_module_id 0x3902 << 16) | 0x2000) 3. in mac initialization routine, right after se tting the emac clock in the pconp register, add a few lines as below: /* turn on the ethernet mac clock in pconp, bit 30 */ regval = pconp; regval |= pconp_emac_clock; pconp = regval; /*------------------------------------------------------ * write to pinsel2/3 to select the phy functions on p1[17:0] * p1.6, enet-tx_clk, has to be set for rev '-' devices and it * must not be set for rev 'a? and newer devices *------------------------------------------------------*/ regval = mac_moduleid; if ( regval == old_emac_module_id ) { /* on rev. '-', mac_moduleid should be equal to old_emac_module_id, p1.6 should be set. */ pinsel2 = 0x50151105; /* selects p1[0,1,4,6,8,9,10,14,15] */ } else { /* on rev. 'a', mac_moduleid should not equal to
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 7 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 old_emac_module_id, p1.6 should not be set. */ pinsel2 = 0x50150105; /* selects p1[0,1,4,8,9,10,14,15] */ } pinsel3 = 0x00000005; /* selects p1[17:16] */ 3.4 ethernet.2: ethernet sram disabled introduction: the lpc2368 has an ethernet interface, which has a dedicated 16 kb sram. problem: when the ethernet block is disabled (in the pconp register located at 0xe01f c0c4), the ethernet sram is also disabled. work-around: enable the ethernet block by setting the pcen et bit (bit no. 30) in the pconp register. the ethernet sram is now enabled. 3.5 ethernet.3: receive stat us registers will not function correctly if rxdescriptor number is greater than 4 introduction: the receive number of descriptors regist er (rxdescriptor-0xffe0 0110) defines the number of descriptors in the descriptor array. each receive descriptor element in the descriptor array has an associated status fiel d which consists of the hashcrc word and status information word. problem: the status words are updated incorrectly if th e number of descriptors set in the receive number of descriptors register is greater than or equal to 5. work-around: define 4 or less in the receive number of descriptors register. 3.6 i2s.1: i 2 s dma interface is non-operational introduction: the lpc2368 has an i 2 s interface, which can be used for audio devices. the i 2 s interface was initially designed to operate with the general purpose dma controller. problem: the dma controller cannot access the i 2 s interface. work-around: no known workaround.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 8 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 3.7 pll.1: pll output (f cco ) is limited to 290 mhz introduction: the pll input, in the range of 32 khz to 50 mh z, may initially be divided down by a value ?n?, which may be in the range of 1 to 2 56. following the pll input divider is the pll multiplier. this can multiply the input divider output through the use of a current controlled oscillator (cco) by a value ?m?, in the range of 1 through 32768. the resulting frequency, f cco must be in the range of 275 mhz to 550 mhz.this frequency can be divided down (using the clock divider registers) to get the desired clock frequencies for the core and peripherals. problem: the maximum output of the cco within the pll block is limited to 290 mhz. work-around: care should be taken while programming the pll so that f cco resides in the desired range. the suggested setting is to use a 12 mh z external crystal. use a plldivider (n) of 1 and pll multiplier (m) of 12. putting the values in the equation: f cco = (2 ? m ? fin) / n f cco = 288 mhz the cpu clock configuration register (located at 0xe01f c104) can then be used to divide this frequency by 4 to produce the maximum cpu speed of 72 mhz (except on rev ?-? and rev ?a?, see flash.1). 3.8 sram.1: 16 kb sram cannot be used for code execution introduction: the lpc2368 has 16 kb of sram on the ahb2 bus, which would generally be used by the ethernet block. problem: the 16 kb of sram can only be used as data ram. code can not be executed from this memory. work-around: no known workaround.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 9 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 3.9 usb.1: usb_need_clk is always asserted introduction: the usb_need_clk signal is us ed to facilitate going into and waking up from chip power down mode. usb_need_clk is asserted if any of the bits of the usbclkst register are asserted. problem: the usb_need_clk bit of the usbintst regi ster (located at 0xe01f c1c0) is always asserted, preventing the chip from entering power down mode when the usbwake bit is set in the intwake register (located at 0xe01f c144). work-around: after setting the pcusb bit in pconp (located at 0xe01f c0c4), write 0x1 to address 0xffe0c008. the usb_need_clk signal will now function correctly. writing to address 0xffe0c008 only needs to be done once after each chip reset. 3.10 usb.2: u1connect si gnal is not functional introduction: u1connect signal (alternate function of p2.9 ) is part of the softconnect usb feature, which is used to switch an external 1.5 kw resistor under the software control. problem: the usb u1connect alte rnate function does not work as expected. work-around: configure p2.9 as a gpio pin, and use it to enable the pull-up resistor on the u1d+ pin. 3.11 usb.3: v bus status input is not functional introduction: the v bus signal indicates the presence of usb bus power. problem: the v bus status input is not functional. work-around: configure p1.30 as a gpio pin, and poll it to determine when v bus goes to 0, signalling a disconnect event.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 10 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 3.12 wdt.1: accessing non-watchdog ap b registers in the middle of the feed sequence causes a reset introduction: the watchdog timer can reset the microcontroller within a reasonable amount of time if it enters an erroneous state. problem: after writing 0xaa to wdfeed, any apb regist er access ot her than writ ing 0x55 to wdfeed may cause an immediate reset. work-around: avoid apb accesses in the middle of the feed sequence. this implie s that interrupts and the gpdma should be disabled while feeding the watchdog. 3.13 core.1: incorrect update of the abort link register in thumb state introduction: if the processor is in thumb state and executing the code sequence str, stmia or push followed by a pc relative load, and the str, stmia or push is aborted, the pc is saved to the abort link register. problem: in this situation the pc is saved to the abor t link register in word resolution, instead of half-word resolution. conditions: the processor must be in thumb state, and the following sequence must occur: <---- data abort on this instruction ldr rn, [pc,#offset] in this case the pc is save d to the link register r14_abt in only word resolution, not half-word resolution. the effect is that the lin k register holds an address that could be #2 less than it should be, so any abort handler co uld return to one instruction earlier than intended. work-around: in a system that does not use thum b state, there w ill be no problem. in a system that uses thumb state but does not use data aborts, or does not try to use data aborts in a recoverable ma nner, there will be no problem. otherwise the workaround is to ensure that a str, stmia or push cannot precede a pc-relative load. one method for this is to add a nop before any pc-relative load instruction. however this is would have to be done manually.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 11 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 3.14 flash.1: operating speed out of on-chip flash is restricted introduction: the operating speed of this device out of internal flash/sram is specified at 72 mhz. problem: code execution from internal flash is rest ricted depending upon the device revision: 1. rev ?a? devices: code execution from intern al flash is restricted to a maximum of 60 mhz. for example, use a pll output frequency of f cco = 360 mhz and divide it by 6 (cclksel = 5) to generate 60 mhz cpu clo ck (do not use even values for cclksel). 2. rev ?-? devices: code execution from internal flash is restricted to a maximum of 60 mhz also. however, this device revision has one more restriction in terms of the pll output frequency (f cco - please refer to pll.1 above). f cco is limited to 290 mhz. considering the same example in pll.1 (input crystal-12 mhz, n = 1, m = 12): f cco =288mhz the cpu clock configuration register (located at 0xe01f c104) can then be used to divide this frequency by 6 (cclksel = 5) to achieve 48 mhz. since this register only accepts odd values for cclksel, a division by 5 (cclksel = 4) is not a valid option. in both the above revisions, code can still execute out of sram at up to 72 mhz. work-around: none.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 12 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 3.15 mam.1: under certain conditions in mam mode 2 code execution out of internal flash can fail introduction: the mam block maximizes the performance of the arm processor when it is running code in flash memory. it includes three 128-bit buffers called the prefetch buffer, the branch trail buffer and the data buffer. it can operate in 3 modes; mode 0 (mam off), mode 1 (mam partially enabled) and mode 2 (mam fully enabled). problem: under certain conditions when the mam is fully enabled (mode 2) code execution from internal flash can fail. the conditions under which the problem can occur is dependent on the code itself along with its positioning within the flash memory. work-around: if the above problem is encountered then mode 2 should not be used. instead, partially enable the mam using mode 1. 3.16 can.1: data overrun condit ion can lock the can controller introduction: each can controller provides a double receive buffer (rbx) per can channel to store incoming messages until they are processed by the cpu. software task should read and save received data as soon as a message reception is signaled. in cases where both receive buffers are fille d and the contents are not read before the third message comes in, a can data overrun situation is signaled. this condition is signaled via the status register and the data overrun interrupt (if enabled). problem: in a data overrun condition, the can controller is locked from further message reception. work-around: 1. recovering from this situation is only possible with a soft reset to the can controller. 2. if software cannot read all messages in time before a th ird message comes in, it is recommend to change the acceptance filtering by adding further acceptance filter group(s) for messages, which are normally rejected. with this approach, the third incoming message is accepted and the da ta overrun condition is avoided. these additional messages are received with the corresponding group index number can be easily identified and rejected by software.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 13 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 3.17 deep power-down.1: deep pow er-down mode is not functional introduction: deep power-down mode is like power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. this produces the lowest possible power consumption without actually removing power from the entire chip. problem: the power consumption in deep power-down mode does not meet the specifications. work-around: none. 3.18 vbat.1: increased power cons umption on vbat when vbat is powered before the 3.3 v supply used by rest of the device introduction: the device has a vbat pin which provides power only to the rtc and battery ram. vbat can be connected to a battery or the same 3.3 v supply used by rest of the device (v dd(3v3) pin, v dd(dcdc)(3v3) pin). problem: if vbat is powered before the 3.3 v supply, vba t is unable to source the start-up current required for the battery ram. therefore, power consumpt ion on the vbat pin will be high and will remain high until 3.3 v supply is pow ered up. once 3.3 v su pply is powered up, power consumption on the vbat pin will reduce to normal and subsequent power cycle on the 3.3 v supply will not cause an increased power consumption on the vbat pin. work-around: provide 3.3 v supply used by rest of the device first and then provide vbat voltage. 3.19 vbat.2: the vbat pin cannot be left floating introduction: the device has a vbat pin which provides powe r only to the real time clock (rtc) and battery ram. vbat can be connected to a batter y or the same supply used by rest of the device (v dd(3v3) pin, v dd(dcdc)(3v3) pin). the input voltage range on the vbat pin is 2.0 v minimum to 3.6 v maximum for temperature ? 40 ? c to +85 ? c. normally, if the rtc and the battery ram are not used, the vbat pin can be left floating. problem: if the vbat pin is left floating, the internal reset signal within the rtc domain may get corrupted and as a result, prevents the device from starting-up. work-around: the vbat should be connected to a battery or th e same supply used by rest of the device (v dd(3v3) pin, v dd(dcdc)(3v3) pin).
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 14 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 3.20 adc.2: external syn c inputs not operational introduction: in software-controlled mode (burst bit is 0) , the 10-bit adc can start conversion by using the following options in the a/d control register: problem: the external start conversion feature, ad0cr: start = 0x2 or 0x3, may not work reliably and adc external trigger edges on p2.10 or p1.27 may be missed. the occurrence of this problem is peripheral clock (pclk) depend ent. the probability of error (missing a adc trigger from gpio) is estimated as follows: ? for pclk_adc = 72 mhz, pr obability error = 12 % ? for pclk_adc = 50 mhz, probability error = 6 % ? for pclk_adc = 12 mhz, probability error = 1.5 % the probability of error is not affected by the frequency of adc start conversion edges. work-around: in software-controlled mode (burst bit is 0), the start conversion options (bits 26:24 set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. the user can also start a conversion by connecting an external trigger signal to a capture input pin (capx) from a timer peripheral to generate an interrupt. the ti mer interrupt routine can then start the adc conversion by setting the start bits (26:24) to 0x1. the trigger can also be generated from a timer match register. fig 1. a/d control register options
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 15 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 4. ac/dc deviations detail 4.1 esd.1: the lpc2368 does not meet the 2 kv esd requirements on the rtcx1 pin introduction: the lpc2368 is rated for 2 kv esd. the rtcx1 pin is the input pin for the rtc oscillator circuit. problem: the lpc2368 does not meet the required 2 kv esd specified. work-around: observe proper esd handling precautions for the rtcx1 pin. 5. errata notes detail 5.1 note.1 on each of the following port pins p0.23, p0 .24, p0.25, p0.26, p1 .30, and p1.31 (when configured as general purpose input pin (s)) , leakage current increases when the input voltage is vi ? v dd i/o + 0.5 v. care must be taken to limit the current to less than 4 ma by using a series limiting resistor. 5.2 note.2 on the lpc2368 rev d, design changes to the memory accelerator module were made to enhance timing and general performance. design changes are intended to enhance performance in general and will result in minor difference s in the code execution timing between the previous device revisions and rev d. actual performance impact is code dependent, some code sequences may speed up while other code sequences may slow down between the previous device revisions and rev d. this might be observed when using software delays and in such cases, a hardware timer should be used to generate a delay instead of a software delay.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 16 of 18 nxp semiconductors es_lpc2368 errata sheet lpc2368 6. legal information 6.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 6.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 6.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners.
es_lpc2368 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. errata sheet rev. 9 ? 20 april 2011 17 of 18 continued >> nxp semiconductors es_lpc2368 errata sheet lpc2368 7. contents 1 product identification . . . . . . . . . . . . . . . . . . . . 3 2 errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 functional problems detail . . . . . . . . . . . . . . . . 5 3.1 ethernet.4: ethernet txconsumeindex register does not update correctly after the first frame is sent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 adc.1: addrx read conflicts with hardware setting of the done bit . . . . . . . . . . . . . . . . . . . 5 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.3 ethernet.1: se tting up the ethernet interface in rmii mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.4 ethernet.2: ether net sram disabled . . . . . . . . 7 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.5 ethernet.3: receive st atus registers will not function correctly if rxdescriptor number is greater than 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 7 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.6 i2s.1: i 2 s dma interface is non-operational . . . 7 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.7 pll.1: pll output (f cco ) is limited to 290 mhz 8 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.8 sram.1: 16 kb sram cannot be used for code execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.9 usb.1: usb_need_clk is always asserted. . 9 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.10 usb.2: u1connect sign al is not functional. . 9 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.11 usb.3: v bus status input is not functional . . . . 9 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.12 wdt.1: accessing non-watchdog apb registers in the middle of the feed sequence causes a reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.13 core.1: incorrect update of the abort link register in thumb state . . . . . . . . . . . . . . . . . . . . . . . . 10 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 conditions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.14 flash.1: operating speed out of on-chip flash is restricted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.15 mam.1: under certain conditions in mam mode 2 code execution out of internal flash can fail . . 12 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.16 can.1: data overrun condition can lock the can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.17 deep power-down.1: deep power-down mode is not functional . . . . . . . . . . . . . . . . . . . . . . . . . 13 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.18 vbat.1: increased power consumption on vbat when vbat is powered before the 3.3 v supply used by rest of the device . . . . . . . . . . . . . . . 13 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.19 vbat.2: the vbat pin cannot be left floating 13 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 13
nxp semiconductors es_lpc2368 errata sheet lpc2368 ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 20 april 2011 document identifier: es_lpc2368 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 3.20 adc.2: external sync inputs not operational . 14 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .14 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .14 4 ac/dc deviations detail . . . . . . . . . . . . . . . . . 15 4.1 esd.1: the lpc2368 does not meet the 2 kv esd requirements on the rtcx1 pin. . . . . . . 15 introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .15 problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .15 5 errata notes detail . . . . . . . . . . . . . . . . . . . . . . 15 5.1 note.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 note.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 legal information. . . . . . . . . . . . . . . . . . . . . . . 16 6.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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